The present invention relates to a semiconductor device having a multi-layer wiring structure made by a damascening process or a dual damascening process, and a method of manufacturing such a device.
An ultra-large scale integrated circuit (ULSI) employs a multilayer wiring structure in which wiring layers of three levels or more are formed.
FIGS. 1 and 2 show a semiconductor device prepared by a conventional wiring process. FIG. 2 is a cross sectional view taken along the line IIxe2x80x94II indicated in FIG. 1.
As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.
On the semiconductor substrate 11, an insulating layer 15 is formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layer 15 from its surface to be through to the source-drain region 13. On the insulating layer 15, a first-level wiring layer having a plurality of wiring layers 17 is formed. Each of the plurality of wiring layers 17 is connected to the source-drain region 13 of the MOS transistor via the contact hole 16.
On the insulating layer 15, an insulating layer (interlayer dielectric) 18 is formed so as to completely cover the plurality of wiring layers 17. A contact hole 19 is made in the insulating layer 18 from its surface to be through to the plurality of wirings 17. On the insulating layer (interlayer dielectric) 18, a second-level wiring layer having a plurality of wiring layers 20 is formed. Each of the plurality of wiring layers 20 is connected to the wiring layers 17 of the first-level wiring layers via the contact hole 19.
On the insulating layer (interlayer dielectric) 18, a bonding pad 21 is formed. Further, on the insulating layer (interlayer dielectric) 18, an insulating layer (passivation dielectric) 22 is formed so as to completely cover the plurality of wiring layers 20 and the bonding pad 21. An opening 23 is made in the insulating film (passivation dielectric) 22 so as to expose the bonding pad 21.
In a semiconductor device manufactured by the conventional wiring process., a plurality of wirings 17 of the first-level wiring layer, a plurality of wirings 20 of the second-level wiring layer and the bonding pad 21 are formed by a photo engraving process (PEP), in which, a resist pattern is formed, and using the resist pattern as a mask, metal layers are etched by an anisotropic etching (such as RIE).
However, in an ULSI, the distance between wirings of the same level is becoming very narrow.
Therefore, the following drawbacks begin to arise.
First, it is very difficult to accurately pattern the wirings 17 and 20 of the wiring layers. This is because the resolution of the exposing device for forming resist patterns, cannot follow up wiring patterns which are becoming finer as the technology develops.
Second, it is very difficult to fill grooves resulting between wirings of the same level, with insulating layer, and therefore cavities are inevitably created between the wirings. This is because of a poor step coverage of the insulating layer. Such cavities adversely affect the multilayer wiring technique.
FIGS. 3 and 4 show a semiconductor device manufactured by a dual damascening process. FIG. 4 is a cross sectional view taken along the line IVxe2x80x94IV indicated in FIG. 3.
As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.
On the semiconductor substrate 11, insulating layers 15 and 24 are formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layers 15 and 24 from its surface to be through to the source-drain region 13.
The insulating layer 25 is formed on the insulating layer 24. In the insulating layer 25, a plurality of grooves 16b used for forming a first-level wiring layer, is formed. Bottom sections of the plurality of grooves 16b are made through to the contact hole 16a. 
A barrier metal 17a is formed on an inner surface of each of the contact hole 16a and the grooves 16. Further, on each of the barrier metals 17a, a metal (or metal alloy) portion 17b is formed so as to completely fill each of the contact hole 16a and the grooves 16b. The plurality of wirings which make the first level wiring layer, consist of the barrier metals 17a and the metal portions 17b. 
The surface of the insulating layer 25 meets with that of the first-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the first-level wiring layer, is connected to the source-drain region 13 of the MOS transistor.
On the insulating layer 25 and the first level wiring layer, the insulating layer (interlayer dielectric) 18 and the insulating layer 26 are formed. A contact hole 19a is formed in the insulating layers 18 and 26 from its surface to be through to the first-level wiring layer.
An insulating layer 27 is formed on the insulating film 26. A plurality of grooves 19b used for forming the second-level wiring layer, are formed in the insulating layer 27. Bottom sections of the plurality of grooves 19b are made through to the contact hole 19a. 
A barrier metal 20a is formed on an inner surface of each of the contact hole 19a and the grooves 19b. Further, on each of the barrier metals 20a, a metal (or metal alloy) portion 20b is formed so as to completely fill each of the contact hole 19a and the grooves 19b. The plurality of wirings which make the second level wiring layer, consist of the barrier metals 20a and the metal portions 20b. 
The surface of the insulating layer 27 meets with that of the second-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the second-level wiring layer, is connected to the first-level wiring layer.
In the case where the second-level wiring layer is located as the uppermost layer, a part of the second-level wiring layer constitutes a bonding pad 21. The bonding pad 21 is made of a metal (or metal alloy), as in the case of the second-level wiring layer.
An insulating layer (passivation dielectric) 22 is formed on the insulation layer 27, the second-level wiring layer and the bonding pad 21. An opening 23 is made in the insulating layer 22 so as to expose the bonding pad 21.
Regarding the semiconductor device manufactured by the dual damascening process as described above, it is able to solve the drawbacks of the conventional wiring process, that is, the wiring pattern becoming out of focus when exposing, and the cavities resulting between wirings.
However, in the dual damascening process or damascening process, the chemical mechanical polishing (CMP) technique is employed. In the case where a bonding pad 21 is formed by the CMP technique, the central portion of the bonding pad 21 is excessively etched, resulting in dishing, that is, the bonding pad 21 is made into a dish-like shape.
FIG. 5 illustrates how dishing occurs.
More specifically, the CMP not only mechanically etch the metal layer 21xe2x80x2, but also chemically etch it. Therefore, in the case where the metal layer 21 (bonding pad) remains in a groove 19b which has a width sufficiently large as compared to its depth (note that the size of a bonding pad is usually about 100 xcexcmxc3x97100 xcexcm), the central portion of the metal layer 21 in the groove 19b is excessively etched mainly by chemical etching.
Such dishing easily causes a bonding error, that is, a wire cannot be bonded to the bonding pad 21 accurately during a wiring bonding operation, which results in the deterioration of the production yield.
FIGS. 6 and 7 show a semiconductor device formed by the dual damascening process, which has been proposed to solve the problem of dishing. FIG. 7 is a cross sectional view taken along the line VIIxe2x80x94VII indicated in FIG. 6.
As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.
On the semiconductor substrate 11, insulating layers 15 and 24 are formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layers 15 and 24 from its surface to be through to the source-drain region 13.
The insulating layer 25 is formed on the insulating layer 24. In the insulating layer 25, a plurality of grooves 16b used for forming a first-level wiring layer, are formed. Bottom sections of the plurality of grooves 16b are made through to the contact hole 16a. 
A barrier metal 17a is formed on an inner surface of each of the contact hole 16a and the grooves 16. Further, on each of the barrier metals 17a, a metal (or metal alloy) portion 17b is formed so as to completely fill each of the contact hole 16a and the grooves 16b. The plurality of wirings which make the first level wiring layer, consist of the barrier metals 17a and the metal portions 17b. 
The surface of the insulating layer 25 meets with that of the first-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the first-level wiring layer, is connected to the source-drain region 13 of the MOS transistor.
On the insulating layer 25 and the first level wiring layer, the insulating layer (interlayer dielectric) 18 and the insulating layer 26 are formed. A contact hole 19a is formed in the insulating layers 18 and 26 from its surface to be through to the first-level wiring layer.
An insulating layer 27 is formed on the insulating film 26. A plurality of grooves 19b used for forming the second-level wiring layer, are formed in the insulating layer 27. Bottom sections of the plurality of grooves 19b are made through to the contact hole 19a. 
A barrier metal 20a is formed on an inner surface of each of the contact hole 19a and the grooves 19b. Further, on each of the barrier metals 20a, a metal (or metal alloy) portion 20b is formed so as to completely fill each of the contact hole 19a and the grooves 19b. The plurality of wirings which make the second level wiring layer, consist of the barrier metals 20a and the metal portions 20b. 
The surface of the insulating layer 27 meets with that of the second-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the second-level wiring layer, is connected to the first-level wiring layer.
In the case where the second-level wiring layer is located as the uppermost layer, a part of the second-level wiring layer constitutes a bonding pad 21. The bonding pad 21 is made of a metal (or metal alloy), as in the case of the second-level wiring layer.
However, in order to prevent the dishing which may occur during the CMP, the bonding pad 21 is formed to have a lattice-like shape. More specifically, in the bonding pad 21, a plurality of dot-like holes which are arranged in a matrix manner are made.
An insulating layer (passivation dielectric) 22 is formed on the insulation layer 27 and the second-level wiring layer. An opening 23 is made in the insulating layer 22 so as to expose the bonding pad 21.
In the semiconductor device manufactured by the dual damascening process, the bonding pad 21 is formed to have a lattice-like shape. Therefore, even in the case where the bonding pad 21 is formed by use of the CMP technique, the necessary portion is not excessively etched, thereby effectively preventing the dishing.
Next, the method of manufacturing a semiconductor device shown in FIGS. 6 and 7 will be described.
First, as can be seen in FIG. 8, with the LOCOS method, a field oxide layer 12 is formed on a silicon substrate 11. After that, in an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14 is formed.
Further, as an alternative, an insulating film (borophospho silicate glass (BPSG) or the like) 15 having a thickness of about 1 xcexcm, which completely covers the MOS transistor, is formed on the silicon substrate 11. The surface of the insulating layer 15 is made flat by the CMP.
Next, as can be seen in FIG. 9, an etching stopper layer 24 and an insulating layer 25 are formed continuously on the insulating film 15 with the CVD method, for example. The insulating layer 25 is made of, for example, silicon oxide. In the case where the insulating layer 25 is made of silicon oxide, the etching stopper layer 24 is made of a material having a high etching selectivity against silicon oxide in reactive ion etching (RIE), that is, for example, silicon nitride.
The thickness of the etching stopper layer 24 is set to about 50 nm, and the thickness of the insulating film 25 is set to the same as that of the wirings which constitute the first-level wiring layer, that is, for example, about 0.6 xcexcm.
Next, as can be seen in FIG. 10, a plurality of grooves 16b are formed in the insulating layer 25. The plurality of grooves 16b are formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 25, the patterning of the resist, the etching of the insulating layer 25 by RIE using the resist as a mask, and the removal of the resist. The etching stopper layer 24 serves as an etching stopper for the RIE.
It should be noted that the pattern of the plurality of grooves 16b is made to match with the pattern of the wirings which constitute the first-level wiring layer.
Next, as can be seen in FIG. 11, a contact hole 16a is made in the insulating layers 15 and 24. The contact hole 16a is made also by the photo engraving process as in the formation of the plurality of grooves 16b. More specifically, the contact hole 16a is made by applying a resist on the insulating layer 25 and in the grooves 16b, patterning the resist, etching the insulating layers 15 and 24 by the RIE using the resist as a mask, and removing the resist.
Then, as can be seen in FIG. 12, a barrier metal 17a is formed on the insulating layer 25, on an inner surface of the contact hole 16a and the inner surfaces of the grooves 16b, by the CVD method or PVD method. The barrier metal 17a is made of, for example, a lamination of titanium and titanium nitride, or silicon titanium nitride, or the like.
Next, as can be seen in FIG. 13, a metal (or metal alloy) portion 17xe2x80x2 which completely covers the contact hole 16a and the grooves 16b, is formed on the barrier metal 17a by the CVD or PVD method. The metal portion 17xe2x80x2 is made of, for example, aluminum, copper or an alloy of these metals.
As the PVD method which is used to form the metal portion 17xe2x80x2, the high temperature PVD method or a PVD method including such a temperature process that can completely fill the contact holes 16a and the grooves 16b, is used.
Next, as can be seen in FIG. 14, the sections of the barrier metal 17a and the metal portion 17b, which are situated outside the contact holes 16a and the grooves 16b, are etched by the CMP method, so that the barrier metal 17a and the metal portion 17b remain only in the contact holes 16a and the grooves 16b. 
In this manner, the first-level wiring layer is formed, and at the same time, a contact plug which serves to electrically connect the first-level wiring layer and the diffusion layer (source-drain region) of the substrate to each other, is formed.
Next, as can be seen in FIG. 15, an insulating layer (for example, silicon oxide) 18 having a thickness of about 1 xcexcm, is formed on the insulating layer 25 and the first-level wiring layer by the CVD method. Further, an etching stopper layer 26 and an insulating layer 27 are formed to be continuous on the insulating film 18 with the CVD method, for example. The insulating layer 27 is made of, for example, silicon oxide. In the case where the insulating layer 27 is made of silicon oxide, the etching stopper layer 26 is made of a material having a high etching selectivity against silicon oxide in reactive ion etching (RIE), that is, for example, silicon nitride.
The thickness of the etching stopper layer 26 is set to about 50 nm, and the thickness of the insulating film 27 is set to the same as that of the wirings which constitute the second-level wiring layer, that is, for example, about 0.6 xcexcm.
Next, as can be seen in FIGS. 16 and 17, a plurality of grooves 19b and 19bxe2x80x2 are formed in the insulating layer 25. The plurality of grooves 19b and 19bxe2x80x2 are formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 27, the patterning of the resist, the etching of the insulating layer 27 by RIE using the resist as a mask, and the removal of the resist. The etching stopper layer 26 serves as an etching stopper for the RIE.
It should be noted that the pattern of the plurality of grooves 19b and 19bxe2x80x2 is made to match with the pattern of the wirings which constitute the second-level wiring layer. The pattern of the grooves 19bxe2x80x2 is the same as that of the bonding pad (lattice-like shape) (in the case where the second-level wiring layer is the uppermost layer).
Further, a contact hole 19a is made in the insulating layers 18 and 26. The contact hole 19a is made also by the photo engraving process as in the formation of the plurality of grooves 19b and 19bxe2x80x2. More specifically, the contact hole 19a is made by applying a resist on the insulating layer 27 and in the grooves 19b and 19bxe2x80x2, patterning the resist, etching the insulating layers 18 and 26 by the RIE using the resist as a mask, and removing the resist.
After that, as can be seen in FIGS. 18 and 19, a barrier metal 20a is formed on the insulating layer 27, on an inner surface of the contact hole 19a and the inner surfaces of the grooves 19b and 19bxe2x80x2, by the CVD method or PVD method. The barrier metal 20a is made of, for example, a lamination of titanium and titanium nitride, or silicon titanium nitride, or the like.
Further, metal (or metal alloy) portions 20b and 21 which completely cover the contact hole 19a and the grooves 19b and 19bxe2x80x2, are formed on the barrier metal 20a by the CVD or PVD method. The metal portions 20b and 21 are made of, for example, aluminum, copper or an alloy of these metals.
As the PVD method which is used to form the metal portions 20b and 21, the high temperature PVD method or a PVD method including such a temperature process that can completely fill the contact hole 19a and the grooves 19b and 19bxe2x80x2, is used.
After that, the sections of the barrier metal 20a and the metal portions 20b and 21, which are situated outside the contact hole 19a and the grooves 19b and 19bxe2x80x2, are etched by the CMP method, so that the barrier metal 20a and the metal portions 20b and 21 remain only in the contact hole 19a and the grooves 19b and 19bxe2x80x2. 
In this manner, the second-level wiring layer and the bonding pad having a lattice-like shape are formed, and at the same time, a contact plug which serves to electrically connect the first-level wiring layer and the second-level wiring layer to each other, is formed.
Next, as can be seen in FIG. 20, a passivation layer 22 is formed on the insulating layer 27, the second-level wiring layer and the bonding pad, by, for example, the CVD method. The passivation layer 22 is made of, for example, silicon oxide.
Next, as can be seen in FIGS. 21 and 22, an opening 23 is formed in the passivation layer 22. The opening 23 is situated so as to the lattice-shaped bonding pad 21, and is formed by a photo engraving process, more specifically, the application of a resist on the insulating layer 22, the patterning of the resist, the etching of the insulating layer 22 by RIE using the resist as a mask, and the removal of the resist.
In the RIE operation for making the opening 23, usually the insulating layer 27 is etched as well since the insulating layers 22 and 27 are made of the same material (for example, silicon oxide).
The feature of the semiconductor device manufactured by the above-described dual damascening process or damascening process is that the metal portion itself which gives rise to wirings is not patterned, but the insulating layer is patterned. Since there is no process for filling the sections between wirings with the insulating layer, no cavities are formed between wirings.
Further, in some cases, copper, which has a low resistance, is used to form wirings; however it is known to be very difficult to perform a patterning on copper. In the dual damascening process or damascening process, the patterning of copper is not carried out, but the wirings are formed by filling grooves of an insulating layer with copper. Thus, the wirings made of copper are realized.
Further, in the dual damascening process, wirings and contact plugs can be formed at the same time, and therefore the production cost can be reduced.
However, in the dual damascening process, the RIE operated to make the opening 23 to expose the bonding pad 21, inevitably serves to etch the insulating layer 27 at the same time. This is because the insulating layers 22 and 27 are made of the same material (for example, silicon oxide) as described above.
In the above-described case, as shown in FIGS. 23 and 24, a wire bonding operation can easily result in that a wire 28 squash the lattice-shaped bonding pad 21, which may cause a bonding error. This is because portions of the lattice-like bonding pad 21 are cavities, which may easily cause the deformation of the bonding pad 21.
The present invention has been proposed as a solution to the above-described drawback of the conventional technique, and the object thereof is as follows. That is, regarding the semiconductor device manufactured by the dual damascening process or damascening process, the bonding pad is formed to have a lattice shape, and the deformation of the lattice-shaped bonding pad is prevented so as to suppress bonding error, thereby improving the reliability and yield of the product.
In order to achieve the above-described object, there is provided, according to the present invention, a semiconductor device including: a bonding pad constituted by a conductive member filled in grooves made in an insulating layer having a flat surface; an etching stopper layer formed on the insulating layer and having an opening to expose the bonding pad; and a passivation layer formed on the etching stopper layer and having an opening to expose the bonding pad.
The grooves of the insulating layer are arranged in a lattice-like shape and the bonding pad has a lattice-like shape. The insulating layer and the passivation layer are made of silicon oxide, and the etching stopper layer is made of silicon nitride.
Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, in which a bonding pad is formed by making grooves in an insulating layer having a flat surface and filling the grooves with a conductive material, the method including the stops of: forming an etching stopper layer on the insulating layer and the bonding pad, the etching stopper layer being made of a material which can be etched selectively with respect to at least a material which is used to form the insulating layer; forming a passivation layer on the etching stopper layer, the passivation layer being made of a material which can be etched selectively with respect to at least the material used to form the etching stopper layer; removing only a portion of the passivation layer, which is situated above the bonding pad; and removing only a portion of the etching stopper layer, which is situated above the bonding pad.
The bonding pad is formed by forming a conductive material layer which completely covers the grooves on the insulating layer, followed by polishing the conductive material layer by the CMP. The passivation layer is etched by the RIE and the etching stopper layer is etched by the RIE or CDE.
As the grooves are filled with the conductive material, the bonding pad and the uppermost wiring layer are formed at the same time.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.